This invention relates to trench-gate semiconductor devices, for example power MOSFETs (insulated-gate field-effect transistors), and to their manufacture using self-aligned techniques to fabricate the devices with compact geometries.
Trench-gate semiconductor devices are known, having a trench-gate in a trench that extends from a source region of a first conductivity type through a channel-accommodating region of a second conductivity type to a drain region of the first conductivity type. United States patent specification U.S. Pat. No. 6,087,224 (our reference PHB34245) discloses an advantageous method of manufacturing such trench-gate semiconductor devices, wherein:
(a) a narrow window is defined by providing sidewall extensions at the sidewalls of a wider window in a first mask at a surface of a semiconductor body,
(b) a trench is etched into the body at the narrow window, and the gate is provided in the trench, and
(c) the source region is provided so as to be self-aligned with the trench-gate by means of the sidewall extensions.
This method permits the use of self-aligned masking techniques in a flexible device process with good reproducibility. In particular, by using the sidewall extensions in different stages, narrow trench-gates can be formed and the source region and a contact window for a source electrode can be determined in a self-aligned manner with respect to this narrow trench. The whole contents of U.S. Pat. No. 6,087,224 are hereby incorporated herein as reference material.
U.S. Pat. No. 6,087,224 discloses various forms of the method. Thus, for example, the source region and/or channel-accommodating region may be provided either before or after forming the trench-gate, either a deep or shallow more highly-doped region may be provided (also in a self-aligned manner) in the channel-accommodating region, either a doped-semiconductor or a metal or silicide material may be used for the gate, and either an oxidised or deposited insulating overlayer may be provided (also in a self-aligned manner) over the trench-gate.
It is an aim of the present invention to provide a modification of such a method, involving a novel sequence of process steps that can provide very good control of the doping concentration of the channel-accommodating region adjacent to the trench and that can provide other advantageous device features in relation thereto.
According to the present invention, there is provided such a method of manufacturing a trench-gate semiconductor device, for example an insulated-gate field-effect device, wherein:
(a) a narrow window is defined by providing sidewall extensions at the sidewalls of a wider window in a first mask at a surface of a semiconductor body,
(b) a trench is etched into the body at the narrow window, and the gate is provided in the trench,
(c) the source region is provided so as to adjoin a sidewall of the trench (and is preferably self-aligned with the trench-gate by means of the sidewall extensions), and
(d) the channel-accommodating region is provided using the following sequence of steps:
removing the sidewall extensions to leave at least a part of the first mask at the surface of the body and to form a doping window between the first mask part and the trench-gate, and
introducing dopant of a second conductivity type into the body at least via the doping window so as to form the channel-accommodating region adjacent to the sidewall of the trench and extending laterally below the first mask part.
By providing a doping window between the first mask part and the trench-gate, such a method in accordance with the present invention permits very good control of the doping concentration of the channel-accommodating region adjacent to the trench, while also permitting the channel-accommodating region to be provided after forming the trench-gate.
The inventors find that this method in accordance with the present invention provides an improvement over the detailed embodiments disclosed in U.S. Pat. No. 6,087,224. Thus, when the doping concentration was provided before etching the trench, it was affected by the subsequent formation of the trench-gate structure. When it was carried out after forming an insulating overlayer over the trench-gate, the doping concentration immediately adjacent the trench was affected by the insulating overlayer.
In a method in accordance with the present invention, the insulating overlayer can be provided after stage (d) in, for example, a self-aligned manner with respect the first mask part. Preferably a simple deposition and etch-back (planarization) process is used, that does not involve high (thermal oxidation) temperatures that might otherwise degrade the previously-provided channel-accommodating region doping. The resulting insulating overlayer may readily be formed over a slightly sunken trench-gate so as to extend inside an upper part of the gate trench. Alternatively or additionally, it may extend laterally from the trench into at least a part of the doping window between the first mask part and the trench-gate. In this way, a well-defined contact window can be defined for the source electrode, and reliable insulation can be provided over the trench-gate and the top corner of the gate trench to avoid short-circuits.
Methods in accordance with the present invention are particularly beneficial for manufacturing compact cellular devices, such as power MOSFETs. Thus, the first mask and its associated windows may have a layout geometry that defines device cells with a respective width to the first mask that is sufficiently small in relation to the lateral extent of the dopant provision in stage (d) as to allow the dopant introduced via the doping windows of the cell to merge together below the first mask.
In some embodiments, a drive-in thermal diffusion may be used to provide the channel-accommodating region dopant to a sufficient extent laterally below the first mask part. However, particularly in devices with sub-micron (less than 1 micrometer) lateral dimensions for this region, a high energy implant with a simple activation anneal can be most advantageous.
Preferably the implantation is carried out at a sufficiently high energy and in a sufficiently high dose that the dopant ions implanted at the doping window are scattered to a desired lateral extent below the first mask part. Preferably, the ion energy is so high that the dopant ions penetrate through the first mask part and are implanted in the underlying portion of the body.
The resulting doping profile can be remarkably uniform beneath the doping window and beneath the first mask part. In this way, the doping profile desired for the channel-accommodating region can be precisely and reproducibly implanted.
In order to control precisely the thickness of the first mask part used in this implantation, a composite first mask may be utilised in earlier stages. Thus, at stage (a) the first mask may comprise an upper layer part (e.g. of oxide) on a lower layer part (e.g. of nitride). This upper layer part may be etched away from the lower layer part before implanting the dopant ions through the lower layer part in stage (d).
Because the channel-accommodating region is provided after the trench-gate, high temperature processes that may be used to form the trench-gate structure (such as, for example, thermal oxidation to form a high-quality gate dielectric) do not affect the subsequently provided doping profile of the channel-accommodating region. Preferably the source doping profile is provided after forming the trench-gate structure so as not to be affected thereby. A simple and convenient way to form the source region is to introduce its doping concentration of the first conductivity type into the body via the doping window of stage (d).
Thus, in a convenient and preferred method in accordance with the invention, the trench is etched in stage (b) through a silicon body portion having a doping concentration of the first conductivity type that extends from the surface into an underlying area to provide a part of the drain region. In the case of an insulated-gate device, the gate dielectric may be formed by depositing an insulating layer on the walls of the trench. However, the gate dielectric layer may be formed by thermal oxidation of the silicon body portion at the walls of the trench. Thus, these earlier steps for forming the trench-gate structure do not disturb the subsequently-provided doping profiles of the source region and channel-accommodating region. Furthermore, the etching of the trench and thermal oxidation at its walls to form a high quality gate dielectric can be carried out in a homogeneous body portion, unaffected by the (subsequently-provided) source and channel region doping concentrations.